Python Generation of AXI Register Definitions

General What was the main intentation behind this project? I've work with Xilinx Vivado for almost 4 years and I was disappointed about the buggy tool chain and the complexity to generate a AXI component with a defined register count and if you will change this you must do the same procedure again and also … Continue reading Python Generation of AXI Register Definitions

VARED – VHDL Automatic Register Extract Definition

General The main purpose for developing this was the definitions of AXI register within a component which can have many slave register. These offset are only known to the hardware developer but not the software developer who can't handle VHDL properly. So I decided to make a defintion how the hardware developer should describe the … Continue reading VARED – VHDL Automatic Register Extract Definition

Tutorial – Setup pyUSB under Windows

General The basic idea was to control different measurement devices, the easy part was RS232 communication with python but for further usage it was necessary to control measurement devices with USB connection too. Requirements pyUSB (https://walac.github.io/pyusb/) libUSB windows package (https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-1.0.20/libusb-1.0.20.7z/download) Usage If you are starting a test program with following content: With this code snippet … Continue reading Tutorial – Setup pyUSB under Windows